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System-Level Test And Validation Of Hardware Software Systems

Matteo Sonza Reorda

  • Categorie: Wetenschap & Natuur
  • EAN: 9781852338992
Inhoud
Taal:en
Bindwijze:Hardcover
Oorspronkelijke releasedatum:03 mei 2005
Aantal pagina's:179
Illustraties:Nee
Betrokkenen
Hoofdauteur:Matteo Sonza Reorda
Tweede Auteur:Peng, Zebo
Co Auteur:Violante, Massimo
Hoofdredacteur:Matteo Sonza Reorda
Tweede Redacteur:Zebo Peng
Co Redacteur:Massimo Violante
Hoofduitgeverij:Springer London Ltd
Overige kenmerken
Editie:2005 ed.
Extra groot lettertype:Nee
Product breedte:155 mm
Product lengte:235 mm
Studieboek:Ja
Verpakking breedte:159 mm
Verpakking hoogte:13 mm
Verpakking lengte:235 mm
Verpakkingsgewicht:386 g


Productbeschrijving

New manufacturing technologies have made possible the integration of entire systems on a single chip. This monograph provides an overview of the validation and test techniques by covering various aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes; and design for testability.

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.

System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;

• stimulus generation for validation and test purposes (including timing errors;

• design for testability.

For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.